1. Field of the Invention
The present invention relates generally to integrated circuits and more particularly to differential sense amplifiers that functions as a preamplifier and a latch circuit.
2. Description of Related Art
Sense amplifiers are typically used to read the state (“0” or “1”) of memory cells in memory arrays, such as read-only memory (ROM) arrays. A ROM array may contain millions of memory cells arranged in rows and columns. The sources of each cell in a column may be connected to a source-column line, and the source-column line for a selected cell may be connected to a reference potential or ground during reading of the selected cell by a sense amplifier. The drains of each cell in a column are connected to a separate bit-line (drain-column line), and the drain-column line for a selected cell is connected to the input of the sense amplifier during reading of the selected cell. The control gates of each cell in a row are connected to a word line, and the word line for a selected cell is connected to the predetermined select voltage during reading of the selected cell.
During the read operation, the current through the selected cell is compared with a reference current to determine whether or not the selected cell is programmed with a “0” or a “1”. The reference circuitry is connected to the input of a first current-sensing amplifier. The output of the first current-sensing amplifier is connected to one side of a differential amplifier. The differential amplifier compares the voltage output of the first current-sensing amplifier with the voltage output of a second sensing amplifier connected to the selected memory cell being read. If the reference-circuitry comprises a memory cell that is essentially the same as the memory cell being read, it is generally necessary to unbalance the current-sensing amplifiers in order to arrive at a reference current between the current of selected cells programmed with a “0” and the current of selected cell programmed with a “1.”
Problems associated with prior art sense amplifiers include sensitivity to noise, the speed is limited by slew rate, and a kickback noise is generated at input during the transitioning from low to high in a clock signal. Accordingly, it is desirable to design a differential sense amplifier that enhances a memory read margin, reduces kickback noise, and increases speed performance.